The present invention relates to a nonvolatile semiconductor memory and a method of fabricating the same and, more particularly, to the structure of a gate electrode in an electrically programmable device and a method of fabricating the same.
Some electrically programmable nonvolatile semiconductor memories have a stacked gate structure including a floating gate electrode, inter-gate insulating film, and control gate electrode, in which an element region is formed in self-alignment with the floating gate electrode, and the inter-gate insulating film is formed on the upper surface and on portions of the side surfaces of the floating gate electrode.
This type of device is conventionally fabricated by the following procedure.
First, a gate insulating film, a polysilicon film serving as a floating gate electrode, and a mask material are formed on a semiconductor substrate. The mask material is patterned by photolithography or the like. The obtained mask material is used as a mask to etch the floating gate electrode and gate insulating film in self-alignment with each other. In addition, the semiconductor substrate is etched to form a groove for an element isolation region.
Subsequently, an insulating film is buried in the element isolation region and planarized by CMP (Chemical Mechanical Polishing) or the like, and the mask material is removed.
The insulating film buried in the element isolation region is etched back to make the upper surface of the insulating film in the element isolation region lower than that of the floating gate electrode.
An inter-gate insulating film is formed, and a polysilicon layer serving as a control gate electrode and a tungsten silicide film are deposited.
The gate electrode is patterned by removing unnecessary portions of the control gate electrode, inter-gate insulating film, and floating gate electrode.
After that, a semiconductor device is completed by forming interlayer dielectric films, contacts, interconnection layers, and the like.
Unfortunately, the conventional nonvolatile memory and the method of fabricating the same have the following problem.
If generally used anisotropic etching is used to etch the inter-gate insulating film subsequently to patterning of the gate electrode, the inter-gate insulating film on the side surface of the floating gate electrode readily remains after the etching because the effective film thickness (vertical component) of the inter-gate insulating film on the side surface is large. If the inter-gate insulating film remains, the floating gate electrode material readily remains when the floating gate electrode is etched after that. If the floating gate electrode material remains, an electrical shortcircuit occurs between adjacent gates, and this causes an operation error of the device.
A reference disclosing the conventional nonvolatile semiconductor memory is as follows.
Yong-Sik Yim, Kwang-Shik Shin, “70 nm NAND Flash Technology with 0.025 μm2 Cell Size for 4 Gb Flash Memory”, Semiconductor R & D Center, Samsung Electronics Co., LTD.